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Nicolici, low power vlsi design phd thesis, N. University of Southampton: University of SouthamptonDoctoral Thesis. Testing low power very large scale integrated VLSI circuits has recently become an area of concern due to yield and reliability problems.
This dissertation focuses on minimising power dissipation during test application at logic level and register-transfer level RTL of abstraction of the VLSI design flow.
The low power vlsi design phd thesis part of this dissertation addresses power minimisation techniques in scan sequential circuits at the logic level of abstraction. A new best primary input change BPIC technique based on a novel test application strategy has been proposed. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by changing the primary inputs such that the smallest number of transitions is achieved.
The new technique is test set dependent and it is applicable to small to medium sized full and partial scan sequential circuits. Since the proposed test application strategy depends only on controlling primary input change time, power is minimised with no penalty in test area, performance, test efficiency, test application time or volume of test data.
Furthermore, it is shown that partial scan does not provide only the commonly known benefits such as less test area overhead and test application time, but also less power dissipation during test application when compared to full scan. To achieve power savings in large scan sequential circuits a new test set independent multiple scan chain-based technique which employs a new design for test DFT architecture and a novel test application strategy, is presented.
The technique has been validated using benchmark examples, and it has been shown that power is minimised with low computational time, low overhead in test area and volume of test data, and with no penalty in test application time, test efficiency, or performance. The second part of this dissertation addresses power minimisation techniques for testing low power VLSI circuits using built-in self-test BIST at RTL.
First, it is important to overcome the shortcomings associated with traditional BIST methodologies. It is shown how a new BIST methodology for RTL data paths using a novel concept called test compatibility classes TCC overcomes high test application time, BIST area overhead, performance degradation, volume of test data, fault-escape probability, and complexity of the testable design space exploration, low power vlsi design phd thesis.
Second, power minimisation in BIST RTL data paths is achieved by analysing the effect of test synthesis and test scheduling on power dissipation during test application and by employing new power conscious test synthesis and test scheduling algorithms. Third, the new BIST methodology has been validated using benchmark examples.
Further, it is shown that when the proposed power conscious test synthesis and test scheduling is combined with novel test compatibility classes simultaneous reduction in test application time and power dissipation is achieved with low overhead in computational time.
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If you continue without changing your settings, we will assume that you are happy to receive cookies on the University of Southampton website. University of Southampton Institutional Repository. Power Minimisation Techniques for Testing Low Power VLSI Circuits PhD Dissertation. Record type: Thesis Doctoral. Abstract Testing low power very large scale integrated VLSI circuits has recently become an area of concern due to yield and reliability problems.
Download 3MB. Download kB. More information Published date: October PURE UUID: dbbcaccb1. Last modified: 29 Jan Contributors Author: N. Download statistics Downloads from ePrints over low power vlsi design phd thesis past year. Library staff additional information.
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